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| - preliminary - e910.27a external adjustable high efficiency pfm step-down converter features ? more than 90% efficiency and 100% duty cycle ? wide input voltage range from 5v to 40v ? integrated 1.6a on-chip p- channel mos power switch ? 12a typical shutdown current ? less than 0.5v drop voltage at 500ma output current ? 0.2v to vinput adjustable output range ? controllable vout via an external reference ? no control loop compensation required ? improved current-limited pfm converter ? maximum operating frequency > 300khz ? power good, reset or watchdog signal ? under-voltage lockout and thermal shutdown ? -40c to 125c junction temperature ? available in thermally enhanced tssop24 package applications ? automotive electronics ? minimum component step-down converter ? sequenceable pol power supply systems ? externally controllable led power supply ? externally controllable power amplifier brief functional description the easy to use hysteretic st ep-down converter provides high efficiency over a wide load and input range with few external components. an advanced pfm control scheme gives this device the bene- fits of a pwm converter with high efficiency at heavy loads, while using very low operating current at light loads to maintain an excellent behaviour over load variation. maximum switching frequency of 300khz permits small exter- nal components and operation to 100% duty cycle allows the lowest possible dropout voltage. for optimal flexibility an exter- nal shunt resistor sets the maximum output current. the converter contains a selectable internal reference with high or low voltage to regulate a wide range of output voltage or output current. the reference for output regulation can also be provided from an external source, like dac. a selectable power good, reset or watchdog signal is provided. an external capacitor sets the reset output pulse duration and / or watchdog trigger time. an optional internal short delay timeout can greatly reduce the losses of the whole application in case of short or overload. very low shutdown and quiescent currents and the wide input voltage range makes the converter ideal for battery powered systems. elmos semiconductor ag specification 1 / 50 03sp0357e.00 05.09.2006 typical application vinput voutput cin rs cdr cout lck rfb1 rfb2 csm dsw enps smon, rsel vsm cdrv rsin swd rlev, wen, wdi,sldy rfex vfb gnd, sgnd, agnd pgnd vs e91027 dac
- preliminary - e910.27a 1 general 1.1 warning ? life support applications policy elmos semiconductor ag is continually working to improve t he quality and reliability of its products. nevertheless, semiconduct or devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. i t is the responsibility of the buyer, when utilizing elmos semiconductor ag products, to observe standards of safety, and to avoid situa - tions in which malfunction or failure of a elmos semiconductor ag product could cause loss of human life, body injury or damage to property. in development your designs, please ensure that el mos semiconductor ag products are used within specified operat- ing ranges as set forth in the most recent products specifications. 1.2 general disclaimer information furnished by elmos semiconductor ag is believed to be accurate and reliable. however, no responsibility is assumed by elmos semiconductor ag for its use, nor for any infringements of patents or other rights of third parties, which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of elmos semiconductor ag. elmos semiconductor ag reserves the right to make corre ctions, modifications, enhancements, improvements, and other changes to the products contained in this datasheet at any time to im prove performance, reliability, or manufacturability without notic e. 1.3 application disclaimer circuit diagrams external to elmos semi conductor ag products are included as a means of illustrating typical applications. con se- quently, complete information sufficient for construction purposes is not necessarily given. the information in the application exam- ples has been carefully checked and is believed to be entirely re liable. however, no responsibility is assumed for inaccuracies . cus- tomers are responsible for their products and applications using elmos semiconductor ag components. furthermore, such infor- mation does not convey to the purchaser of the semiconducto r devices described any license under the patent rights of elmos semiconductor ag or others. information published by elmos se miconductor ag regarding third-par ty products or services does not constitute a license from elmos semiconductor ag to use su ch products or services or a warranty or endorsement thereof. to minimize the risks associated with customer products and app lications, customers should provide adequate design and operating safeguards. 1.4 contact elmos semiconductor ag heinrich-hertz-stra?e 1 d-44227 dortmund germany phone: +49 (0) 231 7549 0 fax.: +49 (0) 231 7549 149 e-mail: info@elmos.de web: www.elmos.de copyright @ 2006 elmos semiconductor ag reproduction, in part or whole, without the prior wri tten consent of elmos semiconductor ag, is prohibited. elmos semiconductor ag specification 2 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a 2 pinout 2.1 pin description name pin no. typ c description rsin1 1 a, i, hv pfm current sense comparator input and source te rminal of internal p-mosfet. connect current- sense resistor between vs and rsin. internal power p-mosfet is turned off when the voltage across this resistor is equal to or greater than the current lim it trip level. external filter for extensive high fre- quency noise may be necessary. rsin2 2 a, i, hv pfm current sense comparator input and source te rminal of internal p-mosfet. connect current- sense resistor between vs and rsin. internal power p-mosfet is turned off when the voltage across this resistor is equal to or greater than the current lim it trip level. external filter for extensive high fre- quency noise may be necessary. cdrv 3 a, o, hv high side linear regulator output. cdrv provides a regulated output voltage that is vdrv below vs. the internal power p-mosfet gate is driven between vs and cdrv. bypass cdrv to vs with a high quality ceramic capacitor. there must be always a capacitor c onnected between vs and cdrv. in rare circuit configurations an external schottky diode must be connected between this pad and pgnd to avoid malfunction through exessive substrat currents. vsp 4 s, hv positive power stage supply input. also acts as a voltage sense point for the internal current sense com- parator. bypass vsp to pgnd with a ceramic capacitor in parallel with a low-esr electrolytic capacitor. vsa 5 s, hv positive analog power supply input. by pass vsa to agnd with a ceramic capacitor. enps 6 d, i, hv shutdown input. connect enps to vs for normal operation. drive enps to false to shut the part in shut- down. in shutdown mode most internal circuits are turned off. the thresholds are cmos level compati- ble and a small pull-down current is drawn. smon 7 d, i, hv active-high smon control input. when smon is false the internal linear regulator is already working and can supply current to an external load. but the rest of the internal circuits are turned off. thermal shutdown is already working. the thresholds are cmos level compatible and a small pull-down current is drawn. use this input for sequencing. vsm 8 a, o internal linear regulator output. vsm provides power to the internal circuity and can supply a specified amount of current to an external load. bypass vsm to agnd with a high quality ceramic and parallel low-esr tantal or equivalent, capacitors. all electrical specifications are valid until vsm is settled only. sgnd 9 s signal ground. sgnd requires a short low noise connection to ensure good load regulation. the internal reference is referred to this ground, so errors at this pin are multiplied by the error comparator. agnd 10 s analog ground. agnd requires a short low noise connection to ensure good vsm regulation. the low drop preregulator powers most of internal circuits. vfb 11 a, i feedback input is the error comparator inverting input, and controls output voltage by adjusting switch duty cycle. vfb also aids power good detection circ uit. connect a resistor divider between voutput, vfb and sgnd for the desired output voltage. in case of outer loop current regulation connect vfb to an external sense resistor. rfex 12 a, i if enabled, external reference input is the error comparator noninverting input reference and controls the voltage voutput. in this case power good, reset and watchdog functions are disabled. err 13 d, o open drain logic true output for indicating an internal fault. errors are vsm under voltage lockout, driver voltage low and asic over temperature. sdly 14 d, i when true, the pfm inserts an additional delay after an overcurrent pulse. the switching frequency decreases due to the larger duty cycl e. this function reduces greatly the power c onsumption in case of a fault. the thresholds are cmos level compatible. rlev 15 d, i when false selects internal high-reference voltage and when true internal low-reference voltage. the thresholds are cmos level compatible. rsel 16 d, i when false selects internal reference generator and when true external reference voltage input at port rfex. the thresholds are cmos level compatible. wdi 17 d, i watchdog trigger input. the rising edge of an input pulse resets the watchdog. this function is with internal references available only. the thresholds are cmos level compatible. elmos semiconductor ag specification 3 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a name pin no. typ c description wen 18 d, i watchdog enable input. when true watchdog function is enabled. this function is with internal referen- ces available only.the thresholds are cmos level compatible. pwgd 19 d, o the pwgd open drain output stays low for undervoltage condition at vfb and in case of internal error. use this output for sequencing or in combination with an external timing capacitor at cdly for reset delay timer function and watchdog timeout. this function is with internal references available only. cdly 20 a, i delay timing capacitor input. connect a timing capacitor between cdly and gnd to set the reset out- put duration and watchdog trigger time. gnd 21 s esd structure and substrat ground return for internal circuits. make a short connection between this port and the other grounds. a low impedance circuit ground plane is highly recommended. pgnd 22 s high current power ground return for internal circ uits. make a short connection between this port, the free-wheel diode, input and output capacitors. due tue high frequency currents, a low impedance circuit ground plane is highly recommended. swd1 23 a, o, hv drain output of the internal power p-mosfet. c onnect the external choke and the free-wheel diode to this port. swd2 24 a, o, hv drain output of the internal power p-mosfet. c onnect the external choke and the free-wheel diode to this port. c d = digital, a = analog, s = supply, i = input, o = output, hv = high voltage (max. 40v) elmos semiconductor ag specification 4 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a 2.2 package pinout exposed pad must be connected to gnd figure 2.2-1: pinout tssop24 adt-1 elmos semiconductor ag specification 5 / 50 03sp0357e.00 05.09.2006 1 4 13 14 15 16 17 12 11 10 9 8 7 6 18 19 20 21 22 23 24 3 5 2 rsin1 rsin2 err sdly rlev rsel wdi wen pwgd cdel gnd pgnd swd1 swd2 sgnd vsm smon enps vsa vsp cdrv rfex agnd vfb exposed pad (bottom) top view - preliminary - e910.27a 3 basic blockdiagram elmos semiconductor ag specification 6 / 50 03sp0357e.00 05.09.2006 figure 3-1: blockdiagram pfm errproc pwrgood mux reference power supply hsdrv vilim enps vfb pwgd vsm rlev rsel smon rfex cdly wdi sgnd pgnd swd1 rsin1 vsp cdrv vr1 vr2 vref uvlo ovtmp vcmp ccmp e91027 wen sdly swd2 rsin2 vsa agnd err gnd - preliminary - e910.27a 4 operating conditions 4.1 absolute maximum ratings stresses beyond those listet under ?absolute maxi mum ratings? may cause permanent damage to the device. these are stress ratings only, and functional oper ation of the device at t hese or any other conditions beyond those indicated above is not implied. expose to absolute maximum rated conditions for extended periods may effect device reliability and are not permitted. agnd, sgnd, pgnd and exposed pad must be soldered to gnd and stand for future reference within text as gnd. vsa and vsp must be always external interconnected a nd stand for future reference within text as vs. rsin1 and rsin2 must be always external interconnected and stand for future reference within text as rsin. swd1 and swd2 must be always external interconnected and stand for future reference within text as swd. parameter condition symbol min. max. unit supply voltage input vs vs -0.3 40 v supply voltage input vs (load dump) tw<400ms vsmax -0.3 45 v vsm to gnd vsm -0.3 5.5 v ivsm ivsm 0 -20 ma cdrv to gnd vcdrvg -0.3 vs v cdrv to vs vcdrv vs-7.0 vs v rsin to vs vrsin vs-1.0 vs+0.3 v irsin irsin 0 2 a swd to gnd vswd -2.0 vs v iswd iswd 0 -2 a enps to gnd venps -0.3 40 v smon to gnd vsmon -0.3 40 v rlev to gnd vrlev -0.3 vsm v rsel to gnd vsel -0.3 vsm v rfex to gnd vrfex -0.3 vsm v sdly to gnd vtoen -0.3 vsm v vfb to gnd vfb -0.3 vsm v cdly to gnd vcdly -0.3 vsm v pwgd to gnd vpwgd -0.3 8 v ipwgd ipwgd 0 4 ma wen to gnd vwen -0.3 vsm v wdi to gnd vwdi -0.3 vsm v err to gnd verr -0.3 8 v ierr ierr 0 4 ma maximum input current in protection circuitry on any pin iprot -10 10 ma esd protection hbm; r=1.5k, c=100pf vesd -1.5 1.5 kv elmos semiconductor ag specification 7 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a parameter condition symbol min. max. unit capacitor between vs and cdrv ceramic (x7r) or better cdr 150 - nf continuous power dissipation derate 7.5mw/c above +20c @ ta = +20c pvtot - 1000 mw continuous power dissipation 1) derate 25mw/c above +105c @ ta = +105c pvtot - 800 mw thermal resistance junction to ambient rtja - 160 k/w thermal resistance junction to ambient 1) pcb heat sink area 500mm2 rtjacld - 40 k/w thermal resistance junction to case rtjc - 5 k/w operating temperature ta -40 125 c junction temperature tj -40 140 c storage temperature tstg -40 150 c 1) package mounted on fr4 50x50x1.5mm3; 70 cu, zero airflow this integrated circuit can be damaged by esd. elmos semiconductor ag recommends that all integrated circuits must be handled with appropriate precautions . failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtile performance degradation to complete device failure. elmos semiconductor ag specification 8 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a 4.2 recommended operating conditions parameters are guaranteed within the range of operating conditions unless otherwise specified. -40c < tj < 125c parameter condition symbol min. max. unit supply voltage 100nf bypass, ceramic (x7r) vs 5 40 v supply bypass capacitance ceramic (x7r) or better cin 100 - nf source impedance at vfb rfb1//rfb2 rvfb - 2 kohm external reference voltage at rfex zi < 2kohm vrfex 0 1.30 v linear regulator bypass capacitance ceramic (x7r) or better csm 1 10 f driver regulator bypass capacitance ceramic (x7r) or better cdr 330 1000 nf err output current verrl < 0.50v ierr 0.2 2 ma pwgd output current vpwgd < 0.50v ipwgd 0.2 2 ma por and wd timing capacitance ceramic (npo / x7r) cdly 0 1 f dsw max. reverse recovery time if/ ir = 2a trr - 30 ns operating temperature range pvtot within limits top - 40 105 c all voltages are referred to gnd, and currents are positive when flowing into the node unless otherwise specified. elmos semiconductor ag specification 9 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a 5 detailed electrical characteristics the electrical characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. typical values represent t he mean values at room temperature, which are rela- ted to production processes. 5.1 supply voltage and currents no. parameter condition symbol min. typ. max. unit 1 input voltage range vs 5 - 40 v 2 shutdown mode current into vs enps=false smon=false vs=>6v ishtd - 12 18 a 3 enps input high threshold 5v - preliminary - e910.27a 5.4 mux no. parameter condition symbol min. typ. max. unit 1 rfex input voltage range 1) vrfex 0 - 1.30 v 2 rfex input current 1) 0v < vrfex < 1.3v irfex - -1 -3 a 3 rfex feedthrough loss 1) 2) source impedance < 2kohm vlrfex - 10 - mv 4 rsel level true 1) 2) vrselh - 0.65xvsm - v 5 rsel level false 1) 2) vrsell - 0.26xvsm - v 6 rsel input current 1) irsel - 1 - a 7 rlev level true 1) 2) vrlevh - 0.65xvsm - v 8 rlev level false 1) 2) vrlevl - 0.26xvsm - v 9 rlev input current 1) irlev - 1 - a 1) vs => 5v, vsm > 4v, enps = true, smon = true, 2) ensured by design. not production tested. 5.5 voltage comparator no. parameter condition symbol min. typ. max. unit 1 effective vfb offset voltage 1) 2) voff -10 0 10 mv 2 vfb input current 1) ivfb - -1 -3 a 3 vfb reference voltage h 1) vr1 1.165 1.200 1.236 v 4 vfb reference voltage l 1) vr2 194 200 206 mv 5 static vfb hysteresis 1) vcmphyst 4 mv 6 vfb propagation time to sw output 2) vs=12v, vr1+/-100mv tj=25c, rsw=50ohm trhfb - 100 - ns 1) vs => 5v, vsm > 4v, enps = true, smon = true, 2) ensured by design. not production tested. 5.6 current comparator no. parameter condition symbol min. typ. max. unit 1 threshold level 1) vclim vs-170m vs-200m vs-230m v 2 propagation time to swd output 2) vs=12v, tj=25c, rs=1.30ohm, rsw=50ohm trhcl - 100 - ns 1) vs => 5v, vsm > 4v, enps = true, smon = true, 2) ensured by design. not production tested. elmos semiconductor ag specification 11 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a 5.7 pulse frequency modulator no. parameter condition symbol min. typ. max. unit 1 minimum sw off-time 1) sdly = false toffm 1.5 2 2.5 s 2 minimum sw off-time 1) sdly = true and ccmp activeted toffms 14 20 26 s 3 minimum sw on-time 1) tonm 0.5 1 1.5 s 4 blanking time 1) 2) tblk - 300 - ns 5 duty cycle 1) 2) dcyc 0 - 100 % 1) vs => 5v, vsm > 4v, enps = true, smon = true, 2) ensured by design. not production tested. 5.8 power stage no. parameter condition symbol min. typ. max. unit 1 on resistance 1) vs-cdrv = 5v rdson - 0.50 0.80 ohm 2 rsin voltage range 1) vrsr vs-1000m vs-200m vs v 3 swd voltage range 1) vswr -2.0 - vs v 4 minimum sink current by internal regulator 1) 2) cdr = 220nf idrvs 5 8 - ma 5 driver lockout voltage 1) 2) cdr = 220nf vdrvl - 3.74 - v 6 driver voltage 1) 2) between vs and cdrv, cdr = 220nf vdrv 4.5 5.20 6.5 v 1) vs => 5v, vsm > 4v, enps = true, smon = true, 2) static value 5.9 error output and optional short detection delay input no. parameter condition symbol min. typ. max. unit 1 sdly level true 1) 2) vsdlh - 0.65xvsm - v 2 sdly level false 1) 2) vsdll - 0.26xvsm - v 3 err open drain voltage range 1) 2) err = false verrh 0 - 6 v 4 err low voltage 1) ierr<= 1ma verrl - 0.50 0.80 v 5 err leakage current 1) verr = 5v ierrl - - 10 a 1) vs => 5v, vsm > 4v, enps = true, smon = true, 2) ensured by design. not production tested. 5.10 power good / reset and watchdog stage no. parameter condition symbol min. typ. max. unit 1 pwgd threshold 1) vpwgdt - 0.90xvfb - v 2 pwgd hysteresis 1) vpwgdy - 0.05xvfb - v 3 pwgd low voltage pwgd = false ipwgd <= 2ma vpwgdl - 0.50 0.80 v 4 pwgd open drain voltage range 2) pwgd = true vpwgdr 0 - 6 v 5 pwgd leakage current vpwgd = 5v ipwgdl - - 10 a elmos semiconductor ag specification 12 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a no. parameter condition symbol min. typ. max. unit 6 minimum required pulse duration at vfb for pwgd response 1) 2) vfb=1.200v overdrive=-250mv int. vref=1.2v cdly = 100nf trec 2 - - s 7 pwgd delay without cdly 1) 2) vfb=1.050v overdrive=+/-200mv int. vref=1.2v cdly = 0nf tpwgd - 40 - s 8 upper reset timing threshold 1) 2) cdly = 100nf vrud 0.75xvsm 0.8xvsm 0.85xvsm v 9 reset saturation voltage 1) 2) cdly = 100nf vrld 0 - 0.5 v 10 reset discharge resistance 1) 2) rrdc - 15 - ohm 11 reset charge current 1) vsm = 5v vcdly=2.5v irstc 9 15 21 a 12 reset delay with cdly 1) 2) vsm = 5v cdly = 100nf 1% trst 15 25 35 ms 13 wen level true 1) 2) vwenh - 0.65xvsm - v 14 wen level false 1) 2) vwenl - 0.26xvsm - v 15 wdi level true 1) 2) vwdih - 0.65xvsm - v 16 wdi level false 1) 2) vwdil - 0.26xvsm - v 17 watchdog trigger pulse duration 1) 2) reaction on trailing edge only twdi 200 - - ns 18 upper watchdog switching threshold 1) 2) cdly = 100nf vwud 0.75xvsm 0.8xvsm 0.85xvsm v 19 lower watchdog switching threshold 1) 2) cdly = 100nf vwld 0.15xvsm 0.2xvsm 0.25xvsm v 20 watchdog charge current 1) vsm = 5v vcdly=2.5v iwdc 9 15 21 a 21 watchdog discharge current 1) vsm = 5v vcdly=2.5v iwdd 1.68 2.80 3.90 a 22 watchdog period 1) 2) vsm = 5v cdly = 100nf 1% twdp 75 125 175 ms 23 watchdog trigger time 1) 2) vsm = 5v cdly = 100nf 1% twdtr 63 105 147 ms 1) vs => 5v, vsm > 4v, enps = true, smon = true, 2) ensured by design. not production tested. 5.11 thermal shutdown no. parameter condition symbol min. typ. max. unit 1 shutdown temperature 1) vs > 5v ktmps - 160 - c 2 hysteresis 1) vs > 5v ktmph - 30 - c 1) ensured by design. not production tested. elmos semiconductor ag specification 13 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a 6 typical performance characteristics shutdown current vs. input volt. and temper ature reference voltages over temperature idle current vs. input voltage and temperature c urrent sense trip level vs. temperature vsm voltage over input voltage and temperat ure swtich on-resistance vs. temperature elmos semiconductor ag specification 14 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a minimum switch on-time vs. temperature p wgd delay vs. capacitance and temperature minimum switch off-time vs. temperatur e wd period vs. capacitance and temperature short case (sdly=1) min. swtich off time vs. temp. elmos semiconductor ag specification 15 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a 7 functional description 7.1 operation 7.1.1 typical application circuit figure 7.1.1-1: typical application circuit 7.1.2 introduction the e910.27 is a user friendly high voltage cmos st ep-down dc-dc converter that provides an external controllable output voltage. it features an internal 500m ohm (typically) p-channel mo s transistor switch for high efficiency over a wide range of input/output volt ages and currents. moreover the converter can be ope- rated over a very wide input supply range from 5v to 40v with typically 12a shutdown and typically 170a stand by current, making them optimal for use in applications as automotive and industrial control. its sophisticated control scheme combines the adv antages of pulse-skipping pulse-frequency modulation (low supply current) and pulse-width modulation (high e fficiency with heavy loads), providing high efficiency over a wide input voltage and output current range. operat ion up to 100% duty cycle allows the lowest possi- ble dropout voltage, which allows a wider input volt age variation. its small size, high switching frequency, and low external parts count minimise the required circuit board area and component cost. a reset signal is generated for a voltage at vfb below a level of vref-15%. the watchdog circuit monitors a connected controller. if there is no positive going edge at the watchdog input wdi within a fixed time, the pwgd output is set low. the delay for power on reset and the maximum permitted watchdog pulse period can be set externally with capacitor cdly. figure 7.1.1-1 shows the e910.27 in a typical application circuit. elmos semiconductor ag specification 16 / 50 03sp0357e.00 05.09.2006 from vsm or voutput for sequencing or reset vinput voutput cin rs cdr cout lck rfb2 rfb1 cdly rpu csm dsw pfm errproc pwrgood mux reference power supply hsdrv vilim enps vfb pwgd vsm rlev rsel smon rfex cdly wdi sgnd pgnd swd1 rsin1 vsp cdrv vr1 vr2 vref uvlo ovtmp vcmp ccmp e91027 wen sdly swd2 rsin2 vsa agnd err gnd - preliminary - e910.27a 7.2 linear regulators 7.2.1 internal power supply the internal high psrr power supply allows the e910.27 to operate from typically 4.5v up to 40v input vol- tage (vsa), while drawing a constant ve ry low quiescent current (ishtd). this allows the use in automotive k30 systems. it is always on and supports the internal regulators, thermal protection circuits, undervoltage lockout circuits and error logic's with stable reference voltages and currents. 7.2.2 vsm regulator the power supply block contains also a short and ther mal protected low quiescent current 5v low drop linear regulator (vsm). it will be switched on via a high level at pin enps. output vsm can provide at minimum 10ma to an external load (e.g. stand by circuits). due to the very wide input level range from 0v to vs max, and cmos compatible thresholds the enps input can be driven by controllers, bus transceivers (e.g. can), k15d applications and used for power sequencing. in smps operating mode (smon=true) the linear regulat or powers the internal smps circuits. when the input voltage vsa goes below about 4v and therefore vsm drops down to the level vclrh the e910.27 enters into undervoltage lockout state, the internal p-channel mos transistor is switched off and the err output goes low. bypass vsm with a good quality capacitor (csm) to the small signal ground. 7.3 device quiscent currents mode enps smon device quiescent current shutdown (idle) 0 0 ishtd vsm on (linear regulator on, not externally loaded) 1 0 ivsmst smps on (not switching) 1 1 idqs 7.4 drv regulator the e910.27 contains a high side hyster etic regulator (cdrv) that contro ls its output to a voltage of vdrv below the positive high side driver input voltage vsp. th is regulator limits the in ternal p-channel mos transi- stor gate swing, provides high gate charge / dischar ge currents, high switching frequency and allowing high input voltage operation without exceeding the internal p-channel mos transistor gate source breakdown vol- tage. if vdrv drops due any case to its lookout vo ltage vdrvl the err output will be set and internal p- channel mos transistor is switched off. bypass cdrv al ways with a good quality temperature stable cera- mic capacitor between vsp and cdrv, otherwise the chip may be damaged. to avoid substrate currents in case of very high temperatures and a fast falli ng edge of the input voltage a schottky diode between cdrv and pgnd may be necessary. 7.5 error output pin err indicates fault conditions of the e910.27. these conditions are: ? under voltage lockout (vsm < vcrh) ? driver voltage low (vdrv < vdrvl) ? chip over temperature (tj > ktmps) elmos semiconductor ag specification 17 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a ? smon input pin low one or more errors switch the err output into high impedance. if the err pin is not used, it should be con- nected to ground. the open drain output can be wired with other signals. 7.6 reference multiplexer a high flexibel feature of the e910.27 is its internal reference multiplexe r. due to the externally selectable mux the user can choose between tw o internal precise temperature compensated or an user provided external reference. via an external reference voltage at pin rfex the output voltage or output current of the smps circuit can be controlled (e.g. for led dimming applications or synchronous output voltage ramp up). keep in mind that in case of disabling vsm (enps=fals e) the esd input structures of pins rfex, rsel, and rlev will clamp to ground. input signals in this mode leads to malfunction of the e910.27 and are therefore not allowed. in any case floating of the three pins mu st be avoided. a save way to supply the logic levels for the multiplexer is for logically ?false? connect to ground and for logically ?true? connect to vsm. use hard wired coding on the pc-board, because changing the mode during operating is not allowed. vcmp connected to rfex rlev rsel vr1 (internal) - 0 0 vr2 (internal) - 1 0 vrext (external) ex. ref input 0 1 7.7 power good, reset generation and watchdog circuitry 7.7.1 pwrgood block depending on external wiring the pwrgood circuit can provide power-good , reset or watchdog behaviour. the pwgd pin open drain output can be wired ?or? to other e910.27. if the pwgd pin is not used it should be connected to gnd. if the external reference input (rfex) is selected via the mux (rsel=true), the whole pwrgood block is automaticly disabled and the pwgd output stays low. for correct behaviour of the pwgd pin, there must be a minimum input voltage at vsa of 4v. 7.7.2 power good and reset timing if the switcher feedback voltage vfb decreases 15% out of nominal regulation value, the external capacitor cdly at pin cdly will be discharged fast by the rese t generator and pin pwgd is set low. if feedback vol- tage vfb rises above the reset threshold, vref-10% , cdly will be charged with a constant current iwdc. after the power on reset time trst the voltage on capacitor cdly reaches vrud and the pwgd output will be set high (high impedance) again. the value of the power on reset time trst can be set within a wide range depending on the capacitance value of cdly. the delay time of power on reset is defined by the c harging time of the external capacitor cdly and can be calculated as follows: [1] for power good behaviour of the circuit only, e.g. in ca se of ramp up sequencing of multiple power supplies, the delay capacitor cdly is omitted. pwgd out put than will react instantaneously (within tpwgd). elmos semiconductor ag specification 18 / 50 03sp0357e.00 05.09.2006 ( ) cdly i wd c vrld vrud trst ? ? = - preliminary - e910.27a figure 7.7.2-1: time response power good and reset generation elmos semiconductor ag specification 19 / 50 03sp0357e.00 05.09.2006 vsm smon vout vpwgd t t t t vs enps 4.5v 4.0v output undefined (cdly=0nf) vpwgd t t output undefined (cdly=100nf) trst trst trst vpwgdt vpwgdy output voltage o.k. voltage drop at input undervoltage at output overload at output shutdown - preliminary - e910.27a 7.7.3 watchdog timing when the voltage on the delay capacitor cdly has reached vwud and pin wen was set high, the watchdog circuit is enabled and discharges cdly with a constant current iwdd. if there is no rising edge detected at the watchdog input, cdly will be discharge down to vwld, then pwgd output will be set low and cdly will be charged again with the current iw dc until vcdly reaches vwud and pin pwgd will be set high (high impedance) again. if a watchdog pulse, rising edge at watchdog input wdi, o ccurs during the discharge period, cdly is char- ged again and the pwgd output stays high. after vcdly has reached vwud, the periodical behaviour starts once more. the watchdog timing is defined by the charging and disc harging time of the external capacitor cdly and can be calculated as follows: [2] figure 7.7.3-1: watchdog behaviour, time response use hard wired coding of wde on the pc-board, bec ause changing the mode during operating is not allo- wed. elmos semiconductor ag specification 20 / 50 03sp0357e.00 05.09.2006 () cdly iwdd vwld vwud twdtr ? ? = () ( ) cdly iwdd iwdc iwdd iwdc vwld vwud twdp ? ? + ? ? = () cdly iwd c vwld vwud twdl ? ? = vout vwdi vcdly vpwgd vwud vwld twdp twdtr twdl t t t t - preliminary - e910.27a 7.8 description of the smps section the e910.27 is a high input-voltage step down (buck) dc-dc converter including an internal robust p-chan- nel mos transistor with a typical resistance of 0.50 ohm. this low on resistance and the possibility of 100% duty cycle assures high efficiency and a minimal dropout even at high output current level and a wide input voltage variation. by means of an on board shunt resistor current in fault conditions is limited. together with the internal temperature supervisor the device is prot ected against accidental output short circuit, to avoids dangerous load damage. if the chip temperature rises higher than a fixed internal threshold (150c with 40 c hysteresis), the power stage is turned off. the e910.27 automatically switches from pwm operat ion at medium and heavy loads to pulse skipping ope- ration at light loads to improve light-load efficiency wit hout an increase in output ripple. the small size, high switching frequency, integrated p-channel mos transistor, and the low parts count minimise the required cir- cuit board area and component costs. the hysteretic control architecture provides for simple design without any control loop stability concerns usi ng a wide variety of external components. the smps part will be switched on by a high level at pin smon. due to the very wide input voltage range from 0v to vs max, and its cmos compatible thresholds the sm on input can be driven by micro-controllers, bus transceivers (e.g. can), k15d applicat ions and can be used for power up sequencing . figure 7.8-1: choke current waveform elmos semiconductor ag specification 21 / 50 03sp0357e.00 05.09.2006 ilck ilck t t iclim ipeak iout = idc iout = idc iclim discontinuous mode (critical boundary) continuous mode toff ton itrough ipeak il ? il ? t1 t3 t2 = iripple il ? - preliminary - e910.27a 7.8.1 operating modes hysteretic control does not require an internal o scillator. switching frequency depends on external compo- nents and operating modes. operating frequency reduces at li ght loads resulting in excellent efficiency com- pared to other architectures. when delivering low output current s, the e910.27 operates in di scontinuous conduction mode (dcm). in case of delivering medium to high output curr ents, the e910.27 operates in pwm continuous conducted mode (ccm). in this mode, current always flows th rough the choke and never ramps to zero. the pulse fre- quency modulator (pfm) adjusts the internal p-channel mos transistor duty cycle to maintain regulation without exceeding the peak switching current set by the external current sense resistor (rs). 7.8.2 100% duty cycle and dropout the e910.27 operates with a duty cycle up to 100%. this feature extends the input voltage range by turning the internal p-channel mos transistor on continuous ly when the supply voltage (vs) approaches the output voltage. this services the load when conventional swit ching regulators with less than 100% duty cycle would fail. dropout voltage is defined as the difference bet ween the input (vinput) and output (voutput) volta- ges when the input is low enough for the output to drop out of regulation. dropout voltage depends on the internal p-channel mos drain to source on resistance, current sense resistor (rs), and choke (lck) series resistance and is proportional to the load current: [3] 7.8.3 discontinuous conduction mode the e910.27 operates in discontinuous conduction mode ( dcm) at light load current. in discontinuous con- duction mode, current through the choke (lck) starts at zero and ramps up to the peak as high as the vol- tage comparator (vcmp) limit , then ramps down to zero. next cycle starts when the vfb voltage reaches the reference voltage. until then, t he choke current remains zero. switching frequency is lower and switching losses reduce. the switching frequency depends on input voltage, output capacitor and output load. the switch waveform (pin swd) can exhibit ringing, wh ich occurs at resonant frequency of the choke and stray capacitance, due to residual energy stored in the core when the commutation diode (dsw) turns off. 7.8.4 continuous mode pfm control behaviour the e910.27 pfm controller has an unique regulation sc heme that allows pwm operation at medium and high output current with automatic switching to pulse skipping mode at lower currents to improve light load efficiency. under medium and heavy load operation, the choke (l ck) current is continuos and the smps part operates in pwm mode. current always flows through the choke and never ramps down to zero. in this condition, the switching frequency is set by either the minimum on- time (tonm), or the minimum off-time (toffm), depending on the duty cycle. the duty cycle is: [4] if the duty cycle is less than 33%, the minimum on-time (tonm) controls the switching frequency. the ope- rating frequency is approximately: elmos semiconductor ag specification 22 / 50 03sp0357e.00 05.09.2006 ( ) lck rs rdson out drop r r r i v + + ? = () choke on max dsw input choke max dsw output rdc rds rs iout vd v rdc iout vd v duty + + ? ? + ? + + - preliminary - e910.27a [5] if the duty cycle is greater than 33%, the off-time (t offm) sets the switching frequency. the operating fre- quency is approximately: [6] in both cases the voltage is regulated by the voltage comparator (vcmp). for low duty cycles (<33%) the internal p-channel mos transistor is turned on for the minimum on-time (tonm), causing fixed on-time ope- ration. during the internal p-channel mos transistor's on- time the output voltage rises. once the internal p- channel mos transistor is turned off, t he voltage drops to the regulation thre shold set by the external voltage divider (rfb1 and rfb2), and another cycle is initiated. for high duty cycles (>33%) the internal p-channel mos transistor remains off for the minimum off-time (t offm) causing fixed off-time operation. in this case the internal p-channel mos transistor remains on, until the output voltage rises to the regulation threshold set by the external voltage divider (rfb1 and rfb2). then the internal p-channel mos transistor turns off for the minimum off-time (toffm) and the next cycle starts. figure 7.8.4-1: relative switchi ng frequency in continuous conduction mode an unique regulation feature of the pfm controller is its automaticly selecti on of fixed on-time or fixed off-ime mode. by switching between fixed on-time and fixed o ff-time operation the e910.27 can operate at high input to output ratios, yet still operate up to 100% duty cycl e for low dropout. when transitioning from fixed on-time to fixed off-time mode, the output voltage drops slight ly due to the output ripple voltage. in fixed on-time ope- ration the minimum output voltage is regulated, while in fixed off-time operation the maximum output voltage is regulated. thus, as the input voltage drops below approximately three times of the output voltage, a decrease in line regulation can be expec ted. the output voltage drop is about: elmos semiconductor ag specification 23 / 50 03sp0357e.00 05.09.2006 duty khz tonm duty fop ? ? 1000 () () duty khz toffm duty fop ? ? ? ? 1 500 1 f r e q u e n c y vi nput duty < 33%, ton = const = tonm duty > 33%, toff = const = toffm - preliminary - e910.27a [7] at light output loads, the choke current is disconti nuous, takes the e910.27 to switch at lower frequencies and decreasing the internal p-channel mos transistor's gate drive and switching losses. under most circum- stances in discontinuous mode the on-time will be fixed to the minimum on-time of tonm. if the choke (lck) inductance value is small or the current sense resistor (rs) is large the current limit will be reached before the minimum on-time (tonm), terminating the on-time and overwrite it. if the impedance of the feedback divider is too high, or t he choke (lck) inductance is too large, or the output capacitance (cout) is too high and equivalent series resi stance (esr) is too low, then the internal p-chan- nel mos transistor remains on longer than the minimu m on-time (tonm) until the output capacitor charges beyond the voltage comparators (vcmp) hysteresis of about vhyst and c ausing the controller to operate in hysteretic mode. operating in hysteretic mode results in lo wer switching frequency operation. [8] the e910.27 requires a certain esr value for proper operat ion. the transition to hysteretic mode occurs at the critical output capacitor esr: [9] in the above equation iripple is the choke ripple current and can be approached, for duty cycle less than 33%, by: [10] where tonm is the minimum on-time for minimum on-time control, or in case of duty cycle greater than 33%: [11] where toffm is the minimum off- time for minimum off-time mode. 7.8.5 leading edge blanking a leading edge blanking timer (tblk) avoids an erratic oper ation through spikes at rsin input while switch- ing on the internal p-channel mos transistor. the same timer suppresses also a quasi-analogue operation of the internal p-channel mos transis tor by means of too small gate driv e pulses. too small gate pulses lead to internal overheating and the complete smps is switched off. elmos semiconductor ag specification 24 / 50 03sp0357e.00 05.09.2006 2 _ ripple op drop v v toffm lck vd v i dsw output ripple ? + ) ( ripple critical i vhyst esr c _ ? ? ? ? ? ? + ? 2 1 1 4 rfb rfb mv vhyst () tonm l c k rds rs iout v v i on max output input ripple ? + ? ? ? ) ( - preliminary - e910.27a 7.8.6 run away at start-up and output short under start-up or output short condi tion, the pfm will switch the inte rnal p-channel mos transistor always on to bring the output voltage in tolerance. when t he voltage across rs caused by the high switch current reaches the threshold level (vclim) of the comparator ccmp, it resets the pfm and therefore the internal p-channel mos transistor is immediatel y switched off. after the fixed off- time (toffm) the internal p-chan- nel mos transistor starts to conduc t again. the required duty cycle in this short circuit situation is: [12] depending on input voltage vs (especially at high input vo ltages), inductance values for the choke, internal p-channel mos transistors on resistanc e and impedance of the rest of exte rnal components it is not always possible to keep the duty to the required small val ue. when this happens the current through the circuit is rising from period to period, until the output voltage r eaches a value for the duty cycle that the e910.27 can handle, or reaches a maximum current, limited by the cu mulated resistances in the buck path only. in this inrush current situation, the exte rnal components may be over stressed and / or the internal thermo protec- tion switches off the whole smps. normally this star t-up time period is very short and the effect takes no matter. to handle this current run away, the user can select wi th pin sdly=true, a longer off-time option (toffms), that takes place the minimum off-time (toffm) in case of triggering the current comparator ccmp only. due to the reduced stored energy per switching cycle, ramp up duration of the whole supply takes somewhat longer. however, be careful there may be combinations of external component values (especially too low or too high inductance values for the choke), wh ich prevents successful start-up of the supply. elmos semiconductor ag specification 25 / 50 03sp0357e.00 05.09.2006 dsw rs pmos input rlck dsw short vd v von v v vd duty + ? ? + - preliminary - e910.27a 8 design information 8.1 design guidelines external component selection is driven by output to i nput voltage ratio (duty cycle), ripple current and maxi- mum output load. the circuit design is an iterative pr ocess and must be carefully proved by testing of your prototype. first calculate the appropriate duty cy cle range for your circuit, then proceed as follows. 8.1.1 output voltage setting the step down converters output voltage is set usi ng the following equation, where rfb2 is connected between the vfb pin and sgnd, and rfb1 is connected between voutput and the vfb pin. [13] where vref is 200mv, 1.2v or externally by user provided in the range of 0v to 1.3v. output voltage ripple causes the output voltage to be higher or lower than set by the resistor divider at the feedback pin vfb. if the application runs with minimum on-time, the ripple (half of the peak to peak value) adds to the output voltage. in the case of working with minimum off-time, the output voltage is lower by the amount of ripple (half of the peak to peak value) at the output. the input bias current at vfb loads the divider, ther efore rfb2 should not be set too high-valued resistor to obtain high accuracy. a divider current of 120a or higher is recommend. the feedback voltage line can be sensitive to noise. avoid inductive coupling to the choke or the switching node, by keeping the vfb trace away from these areas. in some applications, depending on board layout, the capac itance may be too high from pin vfb to gnd. in this case, the internal comparator may not switch fast enough to operate with the minimum on-time or the minimum off-time given in this data sheet. for such applications a small feedforwa rd capacitor (cff) should be added in parallel with rfb1 to speed up the inter nal voltage comparator. on the other hand in some applications, depending on board layout, a small capacitor (some pf) in parallel to rfb2 might be necessary for stable operation. but this c hanges the operating frequency range too. 8.1.2 current sense resistor selection in case of smps ramping up, heavy output load, or s horted output, the current sense comparator ccmp lim- its the peak switching current to vc lim/rs, where rs is the value of the current sense resistor and vclim is the current sense threshold. minimising the peak switching current will increase efficiency and reduce the size and cost of external components. but, since avail able output current is a function of the peak switching current the peak limit must not be set too low. a good value is setting the peak current limit to 1.20 ti mes the maximum load current by calculating the cur- rent sense resistor to: . [14] this takes the normal coke's inductance value toler ance into account. the maximum rms current in con- tinuous operating mode is (take ?r? from the calculations below): elmos semiconductor ag specification 26 / 50 03sp0357e.00 05.09.2006 2 1 1 rfb vref v rfb output ? ? ? ? ? ? ? ? = ? ? ? ? ? ? + ? 2 20 . 1 ripple max min i iout vclim rs - preliminary - e910.27a [15] for 100% duty cycle we get: [16] the current sense resistor's power rating should be: [17] 8.1.3 choosing the choke value the e910.27 operates with a wide range of inductance va lues. the inductance mainly determines the choke current ripple. lower values are chosen to reduce physica l size of the choke. higher values allow more out- put current because they reduce peak current seen by the internal p-channel mos transistor. higher values also reduce output ripple voltage, and core loss. when choosing a choke you might have to consider maximum load current, core and copper losses, allow- able component height, output voltage ripple, emi, fault curr ent in the choke, saturation, and of course, cost. since the choke value determines the output ripple curr ent, you have to decide the ratio of the ripple current to the output current. the ripple current is depending on the duty cycle. take the worst case ripple current value of your application. [18] the core-material losses (magnetic hysteresis loss, eddy-current loss), skin-effect and proximity-effect losses in the conductor and radiation losses increases s ubstantially with increasing ?r?. calculations show, the most optimum choice happens when this ratio ?r? is set between 0.2 and 0.4 at the maximum output cur- rent. often r=0.3 is used. note that this is just a guideline for an economic design. [19] if the converter should work in continous mode, even with the lowest output current, than the ripple ratio must yet be lower: [20] the first step in choke design is to determine the appr opriate operating mode of the e910.27. calculate the minimum inductance value of the c hoke in continuous mode as follows. elmos semiconductor ag specification 27 / 50 03sp0357e.00 05.09.2006 max ripple iout i ? 3 . 0 min ripple iout i ? 2 max ripple max l iout i iout i r = ? = ? ? ? ? ? ? ? ? + ? ? = 12 1 2 r d iout irs max max rms max rms iout irs = 2 _ = - preliminary - e910.27a equation a: [21] equation b: [22] with rdc choke = choke resistance and rds on = p-channel mos transistor ?on? resistance. case a, minimum input voltage determine the duty cycle for minimum input voltage vs. if the duty cycle is greater than 33% take equation a. if the duty cycle is lower than 33% take equation b. case b, maximum input voltage determine the duty cycle for maximum input votage vs. if the duty cycle is greater than 33% take equation a. if the duty cycle is lower than 33% take equation b. compare the calculation results from case a and ca se b and take the highest inductance value. use the next greater standard inductance value. for optimum efficiency, the choke winding's resistance should be not larger than the current sense resistance (rs). calculate peak choke current at worst case to ensure t hat the choke will not saturate over temperature. fer- rite cores saturate abruptly. peak current can be significantly higher than output current. [23] decide if your circuit can tolerate an magnetic open co re geometry like a rod or barrel (drum), which have high magnetic field radiation, or whether it needs a clos ed core like an u-, e- or toroid to prevent emi prob- lems. 8.1.4 choosing the input and the output capacitor choose the input capacitor cin and the output capacitor cout to manage the input and output peak cur- rents with acceptable voltage ripple. the value of the output capacitor depends on the output voltage ripple requirements as well as the maximum voltage deviation during load transients. esr of the output capacitor and the value of the choke are the major source of output voltage ripple, so low esr capacitors are recom- mended. keep in mind that specifically standard aluminiu m electrolytic capacitors have a large esr variation over temperature and lifetime. for good emi behaviour, t he esl of the output capacitor should also be low. output voltage ripple is the sum of contri butions from esl, esr and capacitance value: [24] the output voltage ripple in continuous mode due to the esr is approximately: [25] elmos semiconductor ag specification 28 / 50 03sp0357e.00 05.09.2006 min max sat rs vclim ichoke ? 25 . 1 cval v esr v esl v vout ripple ripple ripple ripple + + = ripple esr ripple i r esr v ? () toffm i rdc iout vd v lck ripple choke max dsw output ? ? + + () tonm i rdc rds rs iout v v lck ripple choke on max output input ? + + ? ? ? ( - preliminary - e910.27a the output capacitance typically increases with load transient requirements. during the time between the load transient and turn-on of the internal p-channel mos transistor, the output capac itor must supply all the current required by the load. this current supplied by the output capacitor results in a voltage drop across the esr that is substrac ted from the output voltage. for a load step from near zero output current (di scontinuous conduction mode) to its maximum (continuous conduction mode), the following equation can be used to calculate the required output capacitance. [26] if the worst case load step is not so extremely lar ge and the e910.27 stays always in continuous conduction mode, a much smaller capacitance value for cout is possible. [27] where i ? l is the change in choke current, therefore minimum i ripple . obtain an output ripple voltage lower t han the system hysteresis (vhyst) is not practical, since the e910.27 will switch at slower frequencies and increases choke ripple current. the output capacitor cout also needs therefore to be at least big enough to handle the worst case rms current through it. [28] estimate the input capacitor capac itance value for a given maximum voltage ripple in continuous mode as follows: [29] in a buck converter the input capacitor cin must ca rry a high rms current because of the currents pulsating nature. the input filter capacitor reduces peak currents drawn from t he power source and reduces noise and voltage ripple at vinput. use a low esr capacitor type. for good emi behaviour, the esl of the input capacitor should be also very low. two or more sma ller value low esr capacitors connected in parallel work often better than a single larger one. place cerami c capacitors very close from vsa and vsp to gnd. in continuous conduction mode, the input capacitor must be able to handle the whole rms current of the con- verter with the worst case duty cycle of your application. [30] elmos semiconductor ag specification 29 / 50 03sp0357e.00 05.09.2006 12 r iout icout max rms ? = cin v v i iout lck cin ripple input ripple max ? ? ? ? ? ? ? ? + ? 2 2 2 ? ? ? ? ? ? ? ? + ? ? ? = 12 1 2 r duty duty iout icin max rms ? ? ? ? ? ? ? ? ? ? ? ? ? output input input ripple output l v v v cval v v i lck cout 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? output input input ripple output ripple max v v v cval v v i iout lck cout 2 2 2 - preliminary - e910.27a these equations are suitable for initial capacitor selecti on. final values should be set by testing of your pro- totype circuit. 8.1.5 catch diode selection the catch diode dsw carries load current during the inte rnal p-channel mos transisto rs off-time. therefore the average diode current is depending on the duty cycle. at high input to output voltage ratios the diode conducts most of the time. the most stressful condi tion for the diode is when the output is shorted. under this condition the diode must safely handle a peak current of: [31] the catch diode maximum forward loss in continuous conduction mode is: [32] where vd dsw is the maximum forward drop from the diode data sheet and idsw avg is the average current at the minimum duty cycle: [33] the reverse (blocking) voltage vrrm of t he catch diode must be at minimum vinput max . the e910.27 high switching frequency requires a high s peed rectifier dsw. the catch diode is the biggest emi source in the circuit. take therefore care of diode selection. surface mount low reverse leakage schottky diodes are recommended for low output voltages . ultra high speed soft recovery rectifiers with reverse recovery times < 30ns should be used for m oderate or high output voltages, where the increased forward drop causes less efficiency degradation. 8.1.6 snubber network design for low output current, in discontinuous conduction mode, the internal p-channel mos transistor turns off, and the energy stored in the inductance would cause osc illations with the parasitic capacitances without a snubber network. typically there are little losses in parasit ic resonant circuits so many cycles of ringing nor- mally occur. this oscillation may be an emi issue. if required an rc snubber will easily damp the ringing. if the snubber resistance is equal to the characterist ic impedance of the resonant circuit then the resonant circuit will be critically damped. once the circuit has been build and is operating, the values of the snubber components may be evaluated experimentally. start with a small value of capacitor csn and place it in the circuit directly ac ross the catch diode dsw, and observe the voltage waveform with and without the capacit or in the circuit. increase the value of the capaci- tor until the frequency of the ringing to be damped has been halved. this is a near optimum value for the capacitor csn since it allows damping very near q=1. add a resistor in series with the snubber capacitor and choose its value for optimum, so that the ringing will be aperiodic damped. [34] where fres = initially measured resonant frequency, and lck = choke inductance. elmos semiconductor ag specification 30 / 50 03sp0357e.00 05.09.2006 min max peak rs vclim idsw ? 2 dsw avg max vd idsw pdsw ? ( ) duty iout idsw max avg ? ? = 1 lck fres rsn ? ? ? 2 - preliminary - e910.27a the amount of power dissipation is independent of the value of the resistor rsn. if the time constant of the snubber network is short compared to the switching peri od of the converter but is long compared to the volt- age rise time, than the loss can be estimated by: [35] with fop = switching frequency of the converter and v input = maximum input voltage. figure 8.1.6-1: discontinuous mode swit ch drain voltage without and with snubber 8.1.7 maximum available output current versus internal losses and operating temperature the internal e910.27 dc-dc converter losses are a co mbination of quiescent device power, dynamic gate driver power and p-channel mos transistors switching losses. in any case the maximum allowed peak drain current of the internal p-channel mos transistor must not exceed iswd. with the maximum continuous output curr ent of the buck converter and the specified maxi- mum operating temperature, the chip temperature mu st be well lower than the thermal shutdown limit. the maximum available output current of the conver ter depends on maximum duty cycle, switching frequency (dynamic losses) and the thermal transfer of the package provided by the external heat sinking (e.g. printed circuit board). elmos semiconductor ag specification 31 / 50 03sp0357e.00 05.09.2006 2 _ input v csn fop rsn p ? ? without snubber aperiodic damped - preliminary - e910.27a the crossover losses are lowest at minimum input volt age. but they are usually a small fraction of the con- duction losses, they can be sometimes ignored. for 100% duty cycle we get the worst case rms current through the internal p-channel mos transistor.the maximum rms current through the switch in continuous conduction mode over duty cycle can be calculated by: [36] the effective on-resistance of the e910.27 over junction tem perature can be approximated by: [37] in continuous conduction mode the total device pow er loss can be approximated using the following equa- tion: [38] where: t on = p-channel mos transistor turn on time t off = p-channel mos transistor turn off time q ds = p-channel mos transis tor gate driver charge typically values for the e910.27 are: t on ~ 20ns t off ~ 30ns q ds ~ 10nq when maximum junction temperature and maximum operati ng temperature are known, their difference indi- cates the permissible junction temperature rise for t he given application. the t hermal resistance path must ensure that the product pdev x rtaj is lower than this difference. the maximum possible device power loss can by calculated by: [39] where: tamax = maximum operating temperature tjmax = maximum save junction temperature, about 135c rtaj = thermal resistance junction to ambient. elmos semiconductor ag specification 32 / 50 03sp0357e.00 05.09.2006 ? ? ? ? ? ? ? ? + ? = 12 1 2 r duty iout ipmos max rms () ( ) ds off on max input rms input tot q t t iout fop v rdson ipmos idqs v pdev + + ? ? ? ? + ? + ? 5 . 0 2 ? ? ? + ? + ) 85 . 2 41 . 1 470 ( 2 j j t t m m rdson rtaj ta tj pdev max max max ? - preliminary - e910.27a figure 8.1.7-1: typical thermal resi stance (rtaj) versus pc-board area always use a ground plane under the step-down converter to minimise interplane coupling and provide the required heat sinking. the typically thermal resist ance for a given pc-board area can be read in the above diagram. by further reducing of the thermal resistanc e due to an additional external heat sinking (e.g. case) a maximum power loss of about 1.6w is possible. elmos semiconductor ag specification 33 / 50 03sp0357e.00 05.09.2006 25 30 35 40 45 50 t h e r m a l r e s i s t a n c e j u n c t i o n t o a m b i e n t [ c / w ] 5 10 15 20 25 30 35 40 45 50 55 heat sink area [cm2] tssop24 adt-1 package 70m cu, copper clad pc-board - preliminary - e910.27a 9 pcb layout considerations the pc board layout is very important in all high- frequency switching converter designs. poor layout can cause switching noise into the feedback signal and may degrade performance and is general the source of heavy emi problems. figure 9-1: typical conver ter schematic for pcb layout for minimal inductance, the wires indicated by hea vy lines should be as wide and short as possible. keep the ground pin of the input capacitor (c5) as close as possible to the anode of the catch diode (d1), snubber network (if there is any) and output capacitor (c1). th is path carries a large ac current. the switching node, the node with the catch diode cathode, choke, and in ternal p-channel mos transistor drain (swd1 & swd2), should be kept short. this node is one of the main sources for radiated emi since it is an ac vol- tage with switching frequency. it is always a good prac tice to use a ground plane in the design of the pc board, particularly at high frequency currents. the three ground pins, agnd, sgnd and gnd, should be c onnected by as short a trace as possible. the ground pins should be tied to the ground plane, or to a la rge ground trace in close proximity to both the vfb divider and then should be connected to pgnd pin and the output capacitor (c1) grounds. the vfb pin is a high impedance node and care should be ta ken to make the vfb trace short to avoid noise pickup, inaccurate regulation and erratic function of the pwgd output. the feedback resistors should be pla- ced as close as possible to the e910.27, with the gr ound of r3 placed as close as possible to the sgnd of the e910.27. avoid inductive coupling to the choke or the switching node, by keeping the vfb trace away from these areas. radiated noise can be decreased by choosing a shielded version for the choke. refer to the e910.27 demo board as an example layout. elmos semiconductor ag specification 34 / 50 03sp0357e.00 05.09.2006 agnd pgnd swd2 swd1 sgnd vsm cdly wde wdi pwgd err vsp vsa enps smon gnd sdly vfb rfex rlev rsel rsin2 rsin1 cdrv e910.27 vin vout d1 l1 c1 c2 c3 c4 c5 r1 r2 r3 keep feedback wiring away from choke flux keep very short separate analog ground from power ground connect exposed pad to analog ground - preliminary - e910.27a 10 applications information elmos semiconductor ag specification 35 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a 10.1 block x1 10.1.1 block diagram figure 10.1.1-1: blockdiagram of block x1 10.1.2 functional description elmos semiconductor ag specification 36 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a 10.2 application gallery figure 10.2-1: p power supply with reset and watchdog figure 10.2-2: p power supply wake-up by can-transceiver elmos semiconductor ag specification 37 / 50 03sp0357e.00 05.09.2006 agnd pgnd swd2 swd1 sgnd vsm cdly wde wdi pwgd err vsp vsa enps smon gnd sdly vfb rfex rlev rsel rsin2 rsin1 cdrv e910.27 vin vout d1 l1 c1 c2 c3 c4 c5 r1 resb c6 trig p r2 r3 r4 vout = 3.3v -> vin = 4.5v to 40v vout = 5.0v -> vin = 6v to 40v agnd pgnd swd2 swd1 sgnd vsm cdly wde wdi pwgd err vsp vsa enps smon gnd sdly vfb rfex rlev rsel rsin2 rsin1 cdrv e910.27 vin vout d1 l1 c1 c2 c3 c4 c5 r1 resb c6 trig p r2 r3 r4 canh canl bat inh can-transceiver !5a stand-by current - preliminary - e910.27a figure 10.2-3: main power supply wake-up by auxiliary cmos processor figure 10.2-4: discontinous mode automotive power supply elmos semiconductor ag specification 38 / 50 03sp0357e.00 05.09.2006 agnd pgnd swd2 swd1 sgnd vsm cdly wde wdi pwgd err vsp vsa enps smon gnd sdly vfb rfex rlev rsel rsin2 rsin1 cdrv e910.27 vin vout d1 l1 c1 c2 c3 c4 c5 r1 r2 r3 port vdd gnd 5v cmos p internal linear regulator can deliver up to 12ma to external cmos p agnd pgnd swd2 swd1 sgnd vsm cdly wde wdi pwgd err vsp vsa enps smon gnd sdly vfb rfex rlev rsel rsin2 rsin1 cdrv e910.27 k30 vout1 d1 l1 c1 c2 c3 c4 c5 r1 resb c6 trig p r2 r3 r5 c8 c7 l2 k15 r5 d2 c10 15a stand-by current vout2 5v c9 r4 - preliminary - e910.27a figure 10.2-5: external programmable power amplifier figure 10.2-6: step-down converter with tracking auxiliary output elmos semiconductor ag specification 39 / 50 03sp0357e.00 05.09.2006 agnd pgnd swd2 swd1 sgnd vsm cdly wde wdi pwgd err vsp vsa enps smon gnd sdly vfb rfex rlev rsel rsin2 rsin1 cdrv e910.27 vin moton d1 l1 c1 c2 c3 c4 c5 r1 r2 - 0 to 100% vout range - 180a stand-by current r3 c6 r4 m dac data vout agnd pgnd swd2 swd1 sgnd vsm cdly wde wdi pwgd err vsp vsa enps smon gnd sdly vfb rfex rlev rsel rsin2 rsin1 cdrv e910.27 vin vout1 d1 l1 c1 c2 c3 c4 c5 r1 pok r2 r3 on vout2 d2 c7 c6 r4 - vout2 tracks vout1 - pout1 must be greater then pout2 - for negative vout2 reverse d2, c7 and secondary winding of l1 - preliminary - e910.27a figure 10.2-7: extremely low stand-by current high efficiency 1a led driver figure 10.2-8: high efficiency step-down 1a led driver with dimming elmos semiconductor ag specification 40 / 50 03sp0357e.00 05.09.2006 agnd pgnd swd2 swd1 sgnd vsm cdly wde wdi pwgd err vsp vsa enps smon gnd sdly vfb rfex rlev rsel rsin2 rsin1 cdrv e910.27 vin ldon d1 l1 c1 c2 c3 c4 c5 r1 r2 led1 led2 - 15a stand-by current - vin = 5v to 40v with one 1a power led - vin = 10v to 40v with two 1a power led agnd pgnd swd2 swd1 sgnd vsm cdly wde wdi pwgd err vsp vsa enps smon gnd sdly vfb rfex rlev rsel rsin2 rsin1 cdrv e910.27 vin ldon d1 l1 c1 c2 c3 c4 c5 r1 r2 led1 led2 diml - 0 to 100% dimming range - 180a stand-by current - vin = 5v to 40v with one 1a power led - vin = 10v to 40v with two 1a power led r3 c6 - preliminary - e910.27a figure 10.2-9: dimmable high current led cluster driver figure 10.2-10: 1a led driver with temperature protection elmos semiconductor ag specification 41 / 50 03sp0357e.00 05.09.2006 agnd pgnd swd2 swd1 sgnd vsm cdly wde wdi pwgd err vsp vsa enps smon gnd sdly vfb rfex rlev rsel rsin2 rsin1 cdrv e910.27 vin ldon d1 l1 c1 c2 c3 c4 c5 r1 r2 led1 led2 diml ledn r3 r4 rn - 0 to 100% dimming range - 180a stand-by current - up to 1.2a total output current - vin = 5.5v to 40v r5 c6 agnd pgnd swd2 swd1 sgnd vsm cdly wde wdi pwgd err vsp vsa enps smon gnd sdly vfb rfex rlev rsel rsin2 rsin1 cdrv e910.27 vin ldon d1 l1 c1 c2 c3 c4 c5 r1 r2 led1 led2 - 15a stand-by current - vin = 5v to 40v with one 1a power led - vin = 10v to 40v with two 1a power led - thermo protection, e.g. above 85c ntc t1 t2 r3 r4 r5 r6 r7 r8 - preliminary - e910.27a figure 10.2-11: power-up sequencing example elmos semiconductor ag specification 42 / 50 03sp0357e.00 05.09.2006 agnd pgnd swd2 swd1 sgnd vsm cdly wde wdi pwgd err vsp vsa enps smon gnd sdly vfb rfex rlev rsel rsin2 rsin1 cdrv e910.27 vin vout1 d1 l1 c1 c2 c3 c4 c5 r1 r2 r3 agnd pgnd swd2 swd1 sgnd vsm cdly wde wdi pwgd err vsp vsa enps smon gnd sdly vfb rfex rlev rsel rsin2 rsin1 cdrv e910.27 vout2 d2 l2 c10 c8 c9 c6 c7 r5 r6 r7 on r4 t on master (vout1) slave (vout2) - preliminary - e910.27a 11 package 11.1 marking 11.1.1 top side elmos (logo) e 910.27a xxx#yww*@ where e / m / t volume production / prototype / test circuit 910.27 elmos project number a version xxx lot number # assembler code yww year and week of fabrication * mask revision number @ elmos internal marking 11.1.2 bottom side no marking elmos semiconductor ag specification 43 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a 11.2 package dimensions thermally enhanced variation figure 11.2-1: package outlines of tssop24 adt-1 elmos semiconductor ag specification 44 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a elmos semiconductor ag specification 45 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a 12 general 12.1 elmos documents qm-nr.: 07pl0009.xx standard qualifikations plan qm-nr.: 07sp0001.xx reliability test methods qm-nr.: 07va0013.xx reliability testing qm-nr.: 07va0005.xx finalpart release for shipment qm-nr.: 07sp0028.xx taping of devices elmos semiconductor ag specification 46 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a 13 record of revisions chapter rev. change and reason for change date released - 1 initial revision 17.11.05 fjp 2 complete rework fjp elmos semiconductor ag specification 47 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a 14 index table of content 1 general............ ........................................................................................................ .......................................2 1.1 warning ? life s upport applicati ons po licy............................................................................... ........2 1.2 general disclaime r........... ............ ............ ...... .............................................................. .........................2 1.3 application disclaimer... ................................................................................................ .........................2 1.4 contac t.................................................................................................................. .................................2 2 pinout..................................................................................................................... ........................................3 2.1 pin de scription.......................................................................................................... .............................3 2.2 pack age pinout ........................................................................................................... ...........................5 3 basic blockdiagram...... ................................................................................................... ...............................6 4 operating conditi ons.......... ............ .......... ...... ................................................................. ..............................7 4.1 absolute maximum ra tings................................................................................................. ..................7 4.2 recommended operating conditi ons............ ............ ............ ............ ...... ................................... ..........9 5 detailed electrical characteristics. ....................................................................................... .......................10 5.1 supply vo ltage and cu rrent s.............................................................................................. .................10 5.2 low drop internal voltage regulat or...................................................................................... .............10 5.3 internal vsm undervoltage lockout lev el............ .......... .......... .................................................. ........10 5.4 mux...................................................................................................................... ...............................11 5.5 voltage com parator....................................................................................................... ......................11 5.6 current co mparator....................................................................................................... ......................11 5.7 pulse fr equency modul ator................................................................................................ .................12 5.8 power stage........... ................................................................................................... ...........................12 5.9 error output and optional short detection dela y input........ ............ ............ ...... .............................. ..12 5.10 power good / reset and wa tchdog stage......... .......................................................................... .....12 5.11 thermal s hutdown........................................................................................................ .....................13 6 typical performance char acteristics........................................................................................ ...................14 7 functional description....... .............................................................................................. .............................16 7.1 operation............. ................................................................................................... .............................16 7.1.1 typical application circ uit............................................................................................ ................16 7.1.2 introduction.... ............ ...... ..................................................................................... .......................16 7.2 linear regulators... ..................................................................................................... .........................17 7.2.1 internal power s upply.................................................................................................. ................17 7.2.2 vsm regulator........ .................................................................................................. ...................17 7.3 device qu iscent cu rrents................................................................................................. ...................17 7.4 drv r egulator ............................................................................................................ .........................17 7.5 error output.......... ................................................................................................... ............................17 7.6 reference mu ltiplexer.................................................................................................... ......................18 7.7 power good, reset gener ation and watchdog ci rcuitry....................................................................18 7.7.1 pwrgood block. ......................................................................................................... ..............18 7.7.2 power good and reset ti ming............. ............ ............ .......... ............................................. .......18 7.7.3 wa tchdog ti ming........................................................................................................ .................20 7.8 description of the smps section.......................................................................................... ...............21 7.8.1 operating modes...... .......... .......... ...... ........................................................................ .................22 7.8.2 100% duty cycle and dropout.... ............ ............ ...... .......................................................... ........22 7.8.3 discontinuous conduction m ode.......................................................................................... .......22 elmos semiconductor ag specification 48 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a 7.8.4 continuous mode pf m control b ehaviour .................................................................................. 22 7.8.5 leading edge blanking.................................................................................................. ..............24 7.8.6 run away at start-up and output short. ........ ......................................................................... ....25 8 design info rmation......................................................................................................... ..............................26 8.1 design gui delines........................................................................................................ ........................26 8.1.1 output voltage se tting................................................................................................. ................26 8.1.2 current sense resistor selection..... .................................................................................. ........26 8.1.3 choosing t he choke va lue............................................................................................... ...........27 8.1.4 choosing the input and the ou tput capacitor.... ........ ................................................................ .28 8.1.5 catch diode selection... .......... .......... ...... ..................................................................... ...............30 8.1.6 snubber network design ...... .......................................................................................... ............30 8.1.7 maximum available output current versus internal losses and oper ating temperature .........31 9 pcb layout cons iderations .................................................................................................. .......................34 10 applications informat ion ................................................................................................. ...........................35 10.1 blo ck x1................................................................................................................ .............................36 10.1.1 block diagram.......... ............................................................................................... ...................36 10.1.2 functional descripti on............. ........ ........................................................................... ...............36 10.2 application gallery..................................................................................................... ........................37 11 package............. ............ ...... .................................................................................... ..................................43 11.1 marking............... .................................................................................................. .............................43 11.1.1 top side....... ....................................................................................................... .......................43 11.1.2 bottom side............... ............................................................................................ ....................43 11.2 package dimensions ............ ...... .................................................................................... ...................44 12 general.............. ..................................................................................................... ....................................46 12.1 elmos documents... ...................................................................................................... ..................46 13 record of revi sions....................................................................................................... ............................47 14 index..................................................................................................................... ......................................48 elmos semiconductor ag specification 49 / 50 03sp0357e.00 05.09.2006 - preliminary - e910.27a table of figures figure 2.2-1: pinout t ssop24 adt-1. ............................................................................................ ...................5 figure 3-1: bl ockdi agram....................................................................................................... .............................6 figure 7.1.1-1: typical application circ uit.................................................................................... ....................16 figure 7.7.2-1: time response power good and reset generati on............. ............ .......... .......... .................19 figure 7.7.3-1: watchdog behaviour, ti me response..... ......................................................................... .......20 figure 7.8-1: choke current wa veform........................................................................................... .................21 figure 7.8.4-1: relative switching fr equency in continuous conduction mode......... ............ ............ ............23 figure 8.1.6-1: discontinuous mode switch drain vo ltage without and with snubber ............ ..... ...................31 figure 8.1.7-1: typical thermal resistance (rtaj) versus pc-board area..... ..............................................33 figure 9-1: typical converte r schematic fo r pcb layout......................................................................... .......34 figure 10.1.1-1: blockdiagram of block x1...... ................................................................................ ................36 figure 10.2-1: p power supply with reset and wa tchdog..... .................................................................... .37 figure 10.2-2: p power supply wake-up by can-transceiver .......... ...........................................................3 7 figure 10.2-3: main power supply wake-up by auxiliary cmos proc essor..... ..............................................38 figure 10.2-4: discontinous mode automotive power suppl y............. .......... .......... .......... ............................ ..38 figure 10.2-5: external programmable power amplifier... ........................................................................ ........39 figure 10.2-6: step-down converter with tr acking auxiliary output.............................................................. ..39 figure 10.2-7: extremely low stand-by current hi gh efficiency 1a led dr iver........ .......................................40 figure 10.2-8: high efficiency step-down 1a led driver with dimming.........................................................40 figure 10.2-9: dimmable high current led cluster driv er........................................................................ .......41 figure 10.2-10: 1a led driver with temperatur e protection............. ......................................................... ......41 figure 10.2-11: power-up sequenci ng example......... ............ ............ ...... ............................................. .........42 figure 11.2-1: package outlines of t ssop24 adt-1............. ............ ............ ............ ...... ........................ ......44 elmos semiconductor ag specification 50 / 50 03sp0357e.00 05.09.2006 |
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